In my last blog item about the FSS project, I explained why I'm reading Edsger W. Dijkstra's "A Discipline of Programming". Most of my FSS time continues to be consumed by that, but in preparation for a June job interview for an Application Development position at Denim Group, I wrapped my mind around Java a little bit by revisiting FSS proper for a few days. It wasn't enough time to make a lot of progress on the project, but it was nice to take a peek. I look forward to putting Dijkstra behind me so I can jump back into FSS with both feet.

starting simulation
Byte memory read still needs to be implemented.

[2] Exit 1
java -d64 -cp classes:JHDL.jar:axis2-adb-1.2.jar:derby.jar:
infovis.jar ...

This error message comes from a SPARC-V9 Standard Reference Model memory access.

At this point in the development of FSS, there is no reason for the reference model to perform a byte-wide access; the reference model should perform only word-wide accesses (i.e. instruction fetches). The access is byte-wide because
referenceProcessor2ReferenceMemoryWidth.get( this )

returns 0. There is no longer a source for that wire (reference model doesn't deal with wires; it is JHDL-independent), so 0 is just a default value.

The reference model should do absolutely nothing until reset. I run some cycles in the DUV before reset just to make a mess of things, but correct behavior is undefined for this phase of simulation, so there is nothing for the reference model to model.

When the reference model does become active, everything it does should be in a separate thread.

In the FullChipTestBench class, I removed the entire block of code around the reference model's byte-wide memory access. This code appeared in the clock method. In fact, I want to avoid doing anything related to the reference model in the clock method. The reference model is to be clock-ignorant.

Rather than describe and justify every change in my notes, I just went on to make several according to the above strategy.

But except for those few days in June (perhaps a week), my FSS time was dominated by Dijkstra, where I have reached Chapter 20. The good news is that the FSS project is now getting the largest share of my Cosmic Horizon time allocation (at the expense of the Verilog-to-JHDL translation project). On the other hand, total Cosmic Horizon time is down since February due to an intensified job search.