Do you remember when I said that "any SPARC-V9 implementation, including the OpenSPARC T1 processor, can be described by a functional/structural model in JHDL" and that "FSS should be able to verify OpenSPARC T1"? In fact, one of the goals of FSS is that it be able to verify any microprocessor that tries to implement SPARC-V9. That is what the Feldstein SPARC-V9 Simulator is for.

Before those of you not interested in FSS stop reading, let me point out that most of my recent work in this area benefits anyone using Icarus Verilog for OpenSPARC T1 synthesis. The work is potentially useful even to those who use Icarus Verilog for synthesis of designs other than OpenSPARC.

The problem with Icarus Verilog has been latch synthesis. See "Asynchronous if statement is missing the else clause." for details. Cosmic Horizon has been contributing to Icarus Verilog to remove this limitation.

On 2007-05-20, I submitted my first patch to Steve Williams, owner of the Icarus Verilog project, explaining that with this patch "Icarus Verilog can recognize that a latch is inferred, instantiate a NetLatch object, and connect it to the circuit".

On 2007-06-23, I submitted a second patch, which "takes us to the point where it is revealed that tgt-vvp needs some work". Cosmic Horizon's interest is solely in the fnf target, so I'm going to leave the vvp (Verilog simulator) work to others.

As Steve explained on 2007-04-13, "Synthesis is still pretty much relegated to the 0.8 branch, and will be that way for a while yet. I've got a variety of BIG simulation tasks that are taking priority." And that's where my latch synthesis patches have been committed, the "v0_8-branch" of Steve's Git repository. Access that repository with:

git clone git://

Or you can wait until Steve merges synthesis with the trunk and releases an Icarus Verilog version with my improvements. Git, by the way, is a revision control application available here.

There is likely more work to be done on the common Icarus Verilog code to get good FNF. If so, you should see another Icarus Verilog contribution from me in the future.

At this point, those not interested in automated translation of Verilog RTL to other hardware description languages and those not interested in FSS can stop reading.

I mentioned before Tom Hawkins's "path from Verilog to ... JHDL". It is a path that passes through Free Netlist Format (FNF). The Icarus Verilog FNF generator included with Confluence 0.10.6 is an essential piece. On 2007-05-12, I saw Tom's message that "Confluence is no longer in development." Well, the Icarus Verilog FNF generator lives on with Cosmic Horizon and I will redistribute it if necessary. I have already made necessary changes to the Icarus Verilog FNF generator locally.

As I have said before, "In order for FSS to be useful for verification of a user-supplied SPARC-V9 design, that design must be modeled in JHDL." You, the potential FSS users may already have a Verilog RTL design (e.g. OpenSPARC T1), in which case it is unlikely that you would spend much time or money on its translation to JHDL just to be able to try FSS. For you, the translation should be automatic and free.