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Incisive Design Team family

Feldstein SPARC-V9 Simulator (FSS)

RTL block-level designs


RTL chip-level designs

structural chip-level designs

standard languages

JHDL

simulation acceleration

would benefit from Java acceleration

testbench automation

automated verification

Assertion-Based Verification (ABV)

Java assert statement (to programmatically implement
preconditions and postconditions or to verify any other
intermediate states that help you ensure your code is working correctly)

Incisive Design Team Simulator


Utilizes single-kernel architecture for efficient verification of models and testbenches based on Verilogฎ, System Verilog, VHDL, SystemCฎ, Property Specification Language (PSL), and Open Verification Library (OVL). HDL analysis, integrated code coverage and powerful interactive debug complete this simulation solution.




  • SystemC is C.


  • OVL, an Accellera standard, is a library of pre-defined
    assertions, implemented in several languages (currently Verilog, SVA, and PSL).


  • PSL, developed by Accellera for specifying properties or
    assertions about hardware designs, is IEEE Std 1850™-2005. PSL aims to be used with multiple electronic system design languages such as VHDL, Verilog, System
    Verilog, SystemC.





  • com.alanfeldstein.sparc.fss.SparcCaseStudy


  • "Simulator kernel" is byucc.jhdl.base.Simulator.


  • verification of models (i.e. SPARC-V9 implementations) based on JHDL


  • JHDL is Java.


  • Java assert statement (to programmatically implement
    preconditions and postconditions or to verify any other
    intermediate states that help you ensure your code is working correctly)


  • HDL can be compiled by javac.


  • In order to measure code coverage, it is necessary (but not sufficient) to have a results database. FSS Version_0-006 introduces a results database.


  • I wasn't planning to work on Requirement 1.8.2.2 so soon, but there is an AssertionError in Sputnik's integer multiplier that prevents release of FSS
    Version_0-006, which is otherwise ready. A waveform view of internal signal activity would help me to debug this problem, so Version_0-006 will have the waveform feature developed up to the point that I can find the cause of the multiplier's AssertionError.



Incisive Design Team Manager (automates and guides the
verification process and then analyzes data, from planning to closure)



  • automated verification


  • com.alanfeldstein.sparc.postsimulation.DisplayAutomatedVerificationResults


  • Coverage-driven random test program generation is envisioned (but not a requirement). Before this can be done, of course, there must be coverage data in the results database.



not even designed specifically to verify microprocessor designs (very wide scope)

designed specifically to verify SPARC-V9 implementations (very narrow scope)



  • Verilog PLI (C language procedural interface provides a means for Verilog HDL users to access and modify data in an instantiated Verilog HDL data structure dynamically)


  • Verilog is not C.


  • In what language is Incisive Design Team Simulator written?





  • JHDL API (Java language object-oriented interface provides a means for JHDL users to access and modify data in an instantiated JHDL circuit design dynamically)


  • JHDL is Java.


  • simulator and Design Under Verification (DUV) written in same language



Incisive Design Team Formal Verifier (provides a formal means of verifying RTL functional correctness with assertions, without the need of testbench simulation)


Incisive Design Team Xtremeฎ series (accelerators/emulators)

would benefit from Java acceleration

expensive

free*

Sun Solaris, HP-UX, Linux

will execute on any computer platform that supports Java

comprehensive plan-to-closure methodology


System Verilog testbench

JHDL testbench

* A feature-limited free version (Requirement 1.3) will always be available, and is being developed far beyond its current capability. In the future, development will be forked, and a full-featured version (Requirement 1.4) will be sold for the price that it commands.