For a long time, I thought Verification Engineers were smarter than Logic Designers. After all, we Verification Engineers could see their mistakes, each one nourishing the image of a group of people that we probably shouldn't be looking up to. And what happens when we debug the design under verification down to the offending line of HDL code? We report the issue along with the source file name and line number. The Logic Designer then types in the correction. It's a lot like dictation.

secretary catching up on dictation

But seriously, I've been doing a lot of logic design lately and I can tell you from firsthand experience that it's not easy. In my opinion, Logic Designers are worthy of our respect and admiration after all.

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