Alan Feldstein's Blog

Incisive Design Team Simulator

Utilizes single-kernel architecture for efficient verification of models and testbenches based on Verilog®, System Verilog, VHDL, SystemC®, Property Specification Language (PSL), and Open Verification Library (OVL). HDL analysis, integrated code coverage and powerful interactive debug complete this simulation solution.

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  SystemC is C.
  


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  OVL, an Accellera standard, is a library of pre-defined
  assertions, implemented in several languages (currently Verilog, SVA, and PSL).
  


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  PSL, developed by Accellera for specifying properties or
  assertions about hardware designs, is IEEE Std 1850™-2005. PSL aims to be used with multiple electronic system design languages such as VHDL, Verilog, System
  Verilog, SystemC.
  

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  com.alanfeldstein.sparc.fss.SparcCaseStudy
  


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  "Simulator kernel" is byucc.jhdl.base.Simulator.
  


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  verification of models (i.e. SPARC-V9 implementations) based on JHDL
  


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  JHDL is Java.
  


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  Java assert statement (to programmatically implement
  preconditions and postconditions or to verify any other
  intermediate states that help you ensure your code is working correctly)
  


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  HDL can be compiled by javac.
  


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  In order to measure code coverage, it is necessary (but not sufficient) to have a results database. FSS Version_0-006 introduces a results database.
  


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  I wasn't planning to work on Requirement 1.8.2.2 so soon, but there is an AssertionError in Sputnik's integer multiplier that prevents release of FSS
  Version_0-006, which is otherwise ready. A waveform view of internal signal activity would help me to debug this problem, so Version_0-006 will have the waveform feature developed up to the point that I can find the cause of the multiplier's AssertionError.
  

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  automated verification
  


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  com.alanfeldstein.sparc.postsimulation.DisplayAutomatedVerificationResults
  


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  Coverage-driven random test program generation is envisioned (but not a requirement). Before this can be done, of course, there must be coverage data in the results database.
  

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  Verilog PLI (C language procedural interface provides a means for Verilog HDL users to access and modify data in an instantiated Verilog HDL data structure dynamically)
  


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  Verilog is not C.
  


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  In what language is Incisive Design Team Simulator written?
  

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  JHDL API (Java language object-oriented interface provides a means for JHDL users to access and modify data in an instantiated JHDL circuit design dynamically)
  


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  JHDL is Java.
  


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  simulator and Design Under Verification (DUV) written in same language