Any SPARC-V9 implementation can be described by a functional/structural model in JHDL. In order for FSS to be useful for verification of a user-supplied SPARC-V9 design, that design must be modeled in JHDL.

Tom Hawkins promises "a path from Verilog to ... JHDL" requiring that the Verilog be constrained to the subset understood by Icarus Verilog. I am doing some trailblazing by attempting to prove Hawkins's assertion with respect to the Verilog RTL model of the OpenSPARC T1 microprocessor. At this point, I am happy to report that a check of the syntax of the OpenSPARC T1 Verilog source using Icarus Verilog was successful. I wish to thank Alexei Duhovich, who worked with me on IBM's POWER6 microprocessor, for his assistance with this task.

Stay tuned for more on this as I continue to push OpenSPARC T1 toward FSS.