Published in August is a SPECfp_base2006 result for the Intel Core 2 Duo E6850 showing that it matches the performance of POWER6. This processor implements Intel 64 Architecture, an extension of the legacy ...

... Intel x86 processor architecture (CISC). In other words, the Intel Core 2 Duo E6850 fetches x86 instructions and must use hardware to translate these instructions into simpler microinstructions before execution. As Grant McFarland writes in Microprocessor Design, "these processors ... pay a price in die area and complexity to do this".

With the POWER6, an implementation of 64-bit PowerPC (RISC), IBM did not need to pay that price. POWER6 fetches simpler instructions. The relatively modern architecture (Intel 8086 was released in 1978, IBM/Motorola PowerPC 601 in 1993) makes more die area available for microarchitectural features that enhance performance.

Yet Intel Core 2 Duo E6850 keeps up, taking the same number of seconds, but fewer clock cycles to complete the same workload.

For a given instruction set architecture, there may be nothing that a microprocessor design can do to reduce the instruction count (although the compiler has an opportunity). CISC admittedly has an advantage here. But getting back to the die area (not to mention power) savings from not having to translate instructions, I want to believe that PowerPC (and SPARC and Itanium) designs can turn that into a much larger IPC (instructions per cycle) advantage.