On Cosmic Horizon's Verilog-to-JHDL translation project (using OpenSPARC T1 as an example of Verilog), we have achieved correct latch synthesis on Icarus Verilog's v0_8-branch. Get this Verilog compiler via anonymous Git cloning.

When Icarus Verilog moved from version 0.8 to version 0.9, the developers broke synthesis. Improvements to synthesis continue to be made on v0_8-branch. Still, there has been no commitment from Steve Williams to bring synthesis forward into the current release. That's why I say v0_8-branch is superior, that's why I promote use of that branch, and that's why I encourage all users of Icarus Verilog synthesis to make their voices heard.

Anyway, why should I care about synthesis? I'm a front-end microprocessor designer, an architecture guy. Why have I contributed to Icarus Verilog synthesis? I've answered these questions before, but I don't do it often enough. I tend to just jump into details of the project in these blog items.

Actually, there are two active Cosmic Horizon projects. The other one is FSS, a SPARC verification environment. You bring us a SPARC microprocessor design and FSS looks for bugs in its SPARC compliance. If your design is written in JHDL, then you're ready for FSS. If it's written in Verilog, then you'll need a Verilog-to-JHDL translator, the subject of this blog item. (In Alan Feldstein's Blog, I generally alternate between the two projects.)

What does Verilog-to-JHDL translation have to do with synthesis and why have these particular tools been chosen? Translating from Verilog to JHDL can be achieved through an intermediate language called Free Netlist Format (FNF), a technology-neutral target. When Icarus Verilog generates FNF, that involves synthesis. It also involves the FNF generator for Icarus (packaged with Confluence). I chose these particular tools because Tom Hawkins and others working with him on Confluence had already employed/developed these tools to form a path from Verilog to JHDL, and I knew of no other pre-existing path. The challenge for me has been to take OpenSPARC T1 down that path. The tool chain needed (and still needs some) work to be able to support that. One of the issues was support for the latches in OpenSPARC T1.

So if you have a SPARC microprocessor design written in Verilog and would benefit from knowing about bugs in its SPARC compliance, then I want to make you a user of Icarus Verilog synthesis.

Now let me tell you how we achieved correct latch synthesis on Icarus Verilog's v0_8-branch, and what I've been working on since.

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