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Category: General
Posted by: afeldstein
MIPS has an opening for a Senior Software Simulator Developer in its Sunnyvale headquarters.


  • As a senior member of the simulation team, you will be a key contributor to the development and support of instruction set simulators and a cycle accurate instruction set simulator using new exciting simulation technologies.
  • You will develop and support example devices for the simulators in C, C++ and SystemC.
  • You will be working closely with processor architects and designers as well as software developers and third-party partners.


  • BSCS or higher with five or more years of experience.
  • Prior simulator experience highly desired.
  • Must have strong C and C++ skill.
  • SystemC experience desired.
  • Having both Windows and Linux development experience is preferred.
  • Must have good knowledge of assembly language (preferably MIPS instruction set).
  • Good knowledge of microprocessor architectures is preferred.
  • Strong problem solving skills.
  • Strong written and verbal communication skills.
  • Strong self-starter and a good team player.

Category: General
Posted by: afeldstein
When should an architectural reference model execute an instruction? How do we synchronize this execution with that going on in the design under verification (DUV)? What we need is some sort of throttle control, but we are challenged by the fact that an architectural reference model, and indeed all of FSS, is to remain ignorant of the implementation details of the DUV.

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