Alan Feldstein's Blog

I released Version_0-005 yesterday, which implements the remaining instructions in the load_add_store.s program listed in my FSS Version_0-004 blog entry. This completes a round-trip datapath, with operands coming from offchip (i.e. simulated memory in the testbench) and arithmetic results emerging from the chip (i.e. stored in simulated memory). Unlike the previous version, for this release I did verify that the execution was correct (for the test cases that I simulated).

A check of the syntax of the OpenSPARC T1 Verilog source using Icarus Verilog was successful. However, Icarus Verilog doesn't know how to synthesize a latch. I am extending Icarus Verilog so that it does.

In doing so, I ran into a problem. The Icarus Verilog source code contains a call to the integral rounding function, lround. I'm developing on Solaris 9. libm.so.1 provides the functions required by those standards supported by the Solaris 9 OS and earlier versions. It does not include lround. libm.so.2 does. It provides the functions required by those standards supported by the Solaris 10 OS (including C99).

Naturally, I want to upgrade to Solaris 10. The Solaris 10 installation program determined that, to upgrade, "Disk Space Reallocation is required. Please go back and select a valid backup media." I have insufficient mass storage on the network for such a backup. Sun has a nice solution with the Sun StorageTek DAT 72 tape drive, but the interface is SCSI, which my Sun Blade 150 workstation lacks. Furthermore, the workstation has been classified as EOL, so I am encouraged to replace it rather than upgrade.

I intend to make a hardware purchase, a system configured to meet development needs.

At a DAC birds-of-a-feather session this summer, "Are Open Source Tools Ready for Open Source Hardware Designs?", it was clear that the OpenSPARC Community is interested in Icarus Verilog. Cosmic Horizon is contributing to Icarus Verilog because of OpenSPARC.

ASF finally released Axis2 Version 1.1 on 2006-11-13! As I stated in a previous post, FSS Version_0-004 and Version_0-005 have been held up by Axis2. (You'll have Version_0-005 any day now.)

Quoting my own notes from 2006-04-01, the goal of FSS Version_0-004 was to "execute a series of instructions in application program; don't have to prove that execution was correct, just that there were no failures." Versions before this one had no program counter, and therefore could only execute programs with a single instruction. Here is an application program that I wrote and am working with:

.register %g2,#scratch
.register %g3,#scratch
.section ".text"
.global main
.align 4
main:
setx addend1,%r5,%r4
ldx [%r4],%r1
setx addend2,%r5,%r4
ldx [%r4],%r2
add %r1,%r2,%r3
setx sum,%r5,%r4
stx %r3,[%r4]

.type main,#function

.section ".data"
.align 8
addend1:
.xword -2828430351432845200
.type addend1,#object
.size addend1,8
addend2:
.xword -4343273150394861700
.type addend2,#object
.size addend2,8
sum:
.skip 8
.type sum,#object
.size sum,8

I said before that "FSS Version_0-005 implements all of the instructions required to start in the RED_state trap table (i.e. the bootstrap loader), jump to the main entry point of an application program, and execute that program." Actually Version_0-004 can do much of that too. As I said, the goal was to execute more than one instruction in the application program. Therefore, Version_0-004 gets through the bootstrap loader, performs the jump, then executes the first two SPARC-V9 instructions in the above program (i.e. the first two of the SPARC-V9 instructions that make up the setx synthetic instruction). Those instructions are 0b00 0000 and 8a11 6001. Cosmic Horizon's SPARC-V9 implementation requires 15 cycles to get that far.

There is an additional dependency in Version_0-004: Axis2 Version 1.1 or higher. Actually, you only need the Axis2 Databinding Framework (ADB). The current URL for that is http://people.apache.org/repo/m1-ibiblio-rsync-repository/org.apache.axis2/jars/axis2-adb-1.1.jar

I am seeking an engineering position in the microprocessor design flow (computer architecture, microarchitecture, logic design), specifically 64-bit cores for high-end UNIX servers. I have over 15 years experience in the Computer and Electronic Product Manufacturing subsector. In 2000, I earned a Bachelor of Science with Honors.